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Burst-Mode PON Controller
With Integrated Monitoring
Block Diagram
DS1863 MEMORY ORGANIZATION
LOWER MEMORY
SDA
I 2 C
EEPROM/SRAM
SRAM RESET
SCL
INTERFACE
ADC CONFIG/RESULTS
SYSTEM STATUS BITS
ALARM/WARNING COMPARISON RESULTS/THRESHOLDS
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 04h
TABLE 05h
V CC
EEPROM
PW1
EEPROM
CONFIGURATION
EEPROM
PW2
EEPROM
MODULATION
EEPROM
TRACKING
GND
V CC
USER MEMORY
AND ALARM
AND
CALIBRATION
USER MEMORY
LUT
ERROR LUT
POWER ON ANALOG
V CC > V POA
MON1
TRAPS
NONMASKABLE
INTERRUPT
TX-F
MON2
MON3
13-BIT
ADC
RIGHT
SHIFT
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
INTERRUPT
MASK
LATCH
ENABLE
INTERRUPT
LATCH
BEN
TEMP
SENSOR
SAMPLE
CONTROL
INTERRUPT
MASK
MAX BIAS
QUICKTRIP
INTERRUPT
LATCH
FETG
MUX
BMD
HBIAS QUICK
TRIP LIMIT
HTXP QUICK
MUX
TRIP LIMIT
LTXP QUICK
TRIP LIMIT
MUX
8-BIT DAC
W/SCALING
DIGITAL APC
INTEGRATOR
13-BIT
DAC
BIAS
APC SETPOINT FROM
TRACKING ERROR TABLE
TX-D
DS1863
MODULATION LOOKUP
TABLE (TABLE 04h)
8-BIT DAC
W/SCALING
MOD
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